In a significant move, AMD has unveiled a long-term collaboration with TSMC, marking a pivotal moment in the semiconductor industry. This partnership will see the production of AMD’s forthcoming EPYC Venice Zen 6 processors, which are set to be the first high-performance computing products leveraging TSMC’s innovative 2nm N2 manufacturing process. These processors are finely tuned with the new Zen 6 and Zen 6C architectures and incorporate TSMC’s revolutionary NanoSheet technology.
The eagerly anticipated 6th generation EPYC processors, codenamed Venice, are slated for launch next year. This announcement coincides with AMD’s confirmation that the 5th generation EPYC processors have been successfully produced and verified at TSMC’s advanced Fab 21 facility located in Arizona, underscoring a major stride in the United States’ aspirations for domestic chip manufacturing.
“TSMC has been a cornerstone partner for numerous years, and our extensive collaboration with their R&D and manufacturing teams has empowered us to deliver cutting-edge products that redefine the limits of high-performance computing,” stated Dr. Lisa Su, Chairman and CEO of AMD. Echoing this sentiment, Dr. C.C. Wei, TSMC’s Chairman and CEO, remarked, “We are honored to have AMD as a leading high-performance computing customer for our 2nm technology and Arizona fab. Together, we are achieving superior performance, power efficiency, and manufacturing yields for high-performance silicon.”
The Venice processors are designed to utilize the SP7 socket and will support either 12 or 16 channels of DDR5 memory. These advancements signify a crucial leap in AMD’s data center processor roadmap, illustrating the transformative impact of the AMD-TSMC alliance on future computing innovations.
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